1. Technical Field
The present invention relates to semiconductor devices in general, and in particular to a method for composing a dielectric thin film within a multilayer semiconductor device. Still more particularly, the present invention relates to a method for forming a low dielectric thermally conductive thin film within a multilayer semiconductor device.
2. Description of the Prior Art
Within an integrated circuit (IC) device, various electrical components are formed on a semiconductor substrate. These electrical components are normally interconnected with metal lines that are typically formed by a combination of processes such as deposition, masking, and etching, collectively referred to as metalization.
Generally speaking, metalization begins with masking, which includes etching small openings called contacts or vias through all upper layers down to the active regions of a substrate. A conductive metal film is then deposited by techniques such as vacuum evaporation, sputtering, or chemical vapor deposition. Thin metals lines may be formed on the upper surface by either one of the following two methods. The first method is by etching a thin metal film (typically aluminum alloy and its barrier stack) with the assistance of a mask. The second method entails etching trenches into the dielectric layer prior to the metal deposition and subsequent removing the unwanted portions of conductive material (typically copper and its barrier stack) by chemical-mechanical polishing.
As chip density increases, a multi-level interconnect structure is generally more desirable than the single-level interconnect structure described above. A multi-level interconnect structure typically begins with a standard metalization process that leaves the surface components partially wired together. Next, a layer of dielectric material is deposited on top of the partially wired structure. Subsequently, a masking step that etches multiple vias down to a first level metal is performed on the dielectric layer. Thereafter, deposition and etching are performed to form a multi-level interconnect structure.
Regardless of the method by which a multi-level interconnect is formed, the use of a material having a very low dielectric property (ie., a dielectric constant of less than 2.5) as a dielectric layer within the multi-level interconnect structure is critical for the performance of an IC device. At one point, porous silica, such as aerogel or xerogel, was being considered by the semiconductor industry as a possible candidate for the dielectric layer because of its low dielectric constant. For example, bulk aerogel has a dielectric constant of approximately 1.0, and xerogel has a dielectric constant of approximately 1.7. However, materials having a low dielectric constant as a group typically also have extremely low thermal conductivity, and porous silica such as aerogel and xerogel are no exception.
One problem that may arise due to the low thermal conductivity of a dielectric layer is that "hot spots" can be formed during wafer processing. For example, during the photoresist pattern exposure and development stage of wafer processing, the interconnect typically heats up; and because the heat cannot be dissipated by the dielectric layer, the photoresist will become very hot around the region of the interconnect. As a result, the photoresist may bubble, burn, or reticulate to a point that can make the patterning process tremendously difficult. As a result, the use of porous silica as a dielectric medium within a semiconductor device is considered as impractical by the semiconductor industry at large.